As microprocessors become faster and smaller, integrated circuitry (IC) becomes more complex and components become more densely packed. IC components are connected by conductive traces and vias (collectively referred to as “interconnects”) though which electrical signals are sent and/or received. Interconnects are typically formed through a damascene process, whereby conductive material is deposited into holes and trenches etched into a semiconductor substrate. The surrounding material electrically insulates each interconnect from neighboring interconnects. However, the dielectric properties of the substrate material enable capacitive coupling between adjacent interconnects, which increases chip power requirements and interferes with signal transmission.
As device dimensions decrease, interconnect dimensions and spacing also decrease, which results in increased current density and resistance along with a greater risk of electromigration, capacitive coupling and RC delay. Furthermore, interconnect material may diffuse into the surrounding dielectric material, reducing the dielectric insulating capacity and enabling crosstalk between adjacent interconnects and components. While diffusion and electromigration may be controlled by encapsulating the interconnect with a barrier layer, the additional barrier material may increase the resistance and dimensions of the interconnect.
Recent innovations address capacitive coupling by incorporating an airgap between neighboring interconnects. Air has an extremely low dielectric constant (about 1, compared to about 4 for silicon dioxide), and therefore more effectively isolates adjacent interconnects than solid dielectric materials.